Implementation of fault tolerance techniques for integrated network interfaces

The increasing demand for safety and mission-critical computational systems to operate in hostile environ- ments, along with the component miniaturization for such systems, have triggered the need for developing fault tolerance techniques to mitigate the incidence of system failures and increase reliability. Communication architec- tures used in computers for aerospace applications are made up of a growing number of processing cores. Some approaches that are proposed in the literature do not meet the communication requirements of future on-board computers composed of multiple cores. Networks-on-Chip are the successors of the bus for multicore interconnec- tion, integrating cores by the means of Network Interfaces. This work discusses the implementation and evaluates the performance of the Hamming encoding, the Triple Modular Redundancy (TMR), and temporal redundancy into the eXtensible Interface for Routing Unit (XIRU) Network Interface. Five scenarios are considered based on the combination of these techniques. Results show that the TMR in FIFO buffers is the most costly technique in terms of area usage, the Hamming code has the highest power dissipation, while the temporal redundancy has the lower operation frequency. Finally, a modified version of XIRU to integrate cores into Network-on-Chip systems with reliability requirements is devised. We intend to use the interface to integrate the cores of future cubesats developed in the FloripaSat project.