Critical area computation based on equidistance line for small layouts

With reduced feature sizes and tighter pitches in deep submicro, yield loss caused by spot defect becomes much more significant in determing manufacturing yield. Successful designs of defect-tolerant chips must rely on the accurate and fast yield prediction. This paper proposes an improved alternative approach based on the equidistance line in L ∞ metric to compute the critical areas. It is very efficient especially for small layouts.