RF potential of a 0.18-/spl mu/m CMOS logic technology

The RF potential of a 0.18-/spl mu/m CMOS logic technology is investigated, and suggestions for an optimization of the frequency responses (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/) and the 1/f-noise based on device layout, bias conditions, and type of gate dielectrics are made. N/sub 2/O gate oxide in place of nitrogen-implanted oxide is proposed to reduce the 1/f-noise, as well as the use of non-epi wafers and a thick top-metal layer for the implementation of high-Q inductors.