Modeling And Implementation of All-Digital Phase-Locked Loop Based on Vernier Gated Ring Oscillator Time-to-Digital Converter

In this thesis, a complete design of an All-Digital Phase-Locked Loop (ADPLL) for RF application is presented. A Vernier gated ring oscillator time-to-digital converter (TDC) is utilized in the proposed ADPLL, and a two-dimension architecture is developed for the TDC to improve latency and dynamic range. The proposed TDC is able to achieve a raw resolution of 5 ps while provides a detection range up to 10 ns. Meanwhile, an LC tank based digitally controlled oscillator (DCO) with three tuning banks is employed to realize fast frequency tuning and fine resolution of 4 KHz. The simulation on the presented ADPLL predicts an output frequency ranging from 3 GHz to 6 GHz with a reference input of 50 MHz.