An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators

This paper proposes an offset calibration method for dynamic comparators, which trims the effective transconductance of transistors. The proposed offset calibration method requires additional switches only on the fixed-voltage nodes; therefore, it has negligible impact on the comparator's key performances, such as comparison and reset speed, input referred noise, and power consumption. The proposed offset calibration method is verified with a 14-nm FinFET technology. The simulation results show that the standard deviation of the comparator offset is reduced from 2.07 mV to 0.26 mV. With a 6-bit digital controller, the offset tuning range and step size are 20.8 mV and 0.3 mV, respectively. The offset tuning range is approximately 5 times wider than the uncalibrated offset standard deviation. The degradation of the speed, noise, and power efficiency due to the calibration circuits are less than 0.72%.