FPGA Based Design of Integer 2D-DWT in CCSDS Standard

The core standard recommended by CCSDS for spatial digital image compression(CCSDS 122.0-B-1) includes a three-level discrete wavelet transform(DWT),which is suitable for the implementation on logical circuit.In this article,the features of 9/7 integer DWT are introduced and a fast implementation method based on FPGA is proposed.In this method,a number of pieces of on-chip Block RAM are used as cache for row-transformed data so that the row transform and column transform can be processed simultaneously.The method saves logic cells and produces a high data throughput.In addition,based on the method,two kinds of multi-level DWT implementation architectures are given and the availability is verified by simulations.