PPAC scaling enablement for 5nm mobile SoC technology

We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for better short channel control and stronger drive. We suggest SiGe P-channel by Ge Condensation for intrinsic mobility improvement and substrate strain, conformal wraparound contact (CWAC) to reduce contact resistance with minimum parasitic capacitance penalty, metal gate (MG) stressor to improve N-channel mobility, EUV single exposure metal patterning with improved tip-to-tip patterning technique for maximum mask count reduction, and Al metallization to reduce metal & via resistances, however still requiring a validation of the proposed electromigration (EM) risk mitigation. We show that finFET can still be extended to 5nm technology to meet Power-Performance-Area-Cost (PPAC) targets. EGAA NW could enable further 50mV less supply voltage to significantly improve 5nm PPAC scaling.