UVM-based verification methodology for RFID-enabled smart-sensor systems

Universal verification methodology (UVM) is a standardized methodology for verifying integrated circuit designs. In this contribution, we present a UVM-based verification methodology for verifying mixed-signal smart-sensor systems. Our approach permits the validation of system functionality before implementation and also to verify the implementation on various levels of abstraction. The model-based verification approach enables to build a scalable and reusable framework, in which assertions and constrained-random stimuli are used to monitor and also to verify mixed-signal-system behavior automatically. A comprehensive example of an radio-frequency identification-based smart-sensor mixed-signal system used for bioanalytical applications is presented. Along with the designed UVM test bench architecture, we describe a novel solution for estimating the power consumption of the digital sub-system using application-specific random-activity patterns generated during UVM test bench runs (Neumann et al., Synthesis Modelling Analysis and Simulation Methods and Application to Circuit Design, SMACD, 2012).