In-situ Investigation of the Impact of Externally Applied Vertical Stress on III-V Bipolar Transistor

This work presents a new methodology to investigate in-situ the impact of vertical stress on the electrical characteristics of semiconductor devices. It is applied for the first time on III-V Heterojunction Bipolar Transistors (HBT). It combines a nanoindenter, which is used to apply controlled vertical forces on the sample surface, with in-situ electrical measurements using micro probes. The HBT devices are shown to be significantly affected by vertical stress: both the current and the capacitance show a reduction with increasing compressive vertical stress. The observations are confirmed by TCAD simulations This method can be employed to extract the sensitivity of advanced devices to vertical (out-of-plane stress) which is a growing concern in packaging and 3D integration.