Enhanced Compensation for Voltage Regulators Based on Three-Stage CMOS Operational Amplifiers for Large Capacitive Loads

This work presents a compensation technique for a three-stage operational amplifier that is derived from nested Miller compensation and comprises a voltage gain stage in the inner compensation path. The voltage gain k of this stage is able to both increase the Miller effect across the inner compensation capacitor and reduce the high-frequency impedance of the output node when compared to the case of standard nested Miller compensation. As a consequence, the gain-bandwidth product is k times higher, while the inner and the outer compensation capacitors are reduced by a factor k2 and k, respectively. The proposed compensation technique was applied to a three-stage operational amplifier used to implement a voltage regulator: simulations of the regulator showed a significant improvement of slew rate, settling time, and transient output voltage drop when a load current is suddenly requested.