Maximizing scan pin and bandwidth utilization with a scan routing fabric

Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data bandwidth utilization. Herein is presented a flexible switching network called the Scan Routing Fabric (SRF) which can connect any set of tiles' scan channels to available SOC pins in order to facilitate optimal scheduling of tile patterns by box-packing algorithms. Other planned improvements to be integrated with the SRF, such as MICTAM, and independent mode are also discussed. Results from deployment on the latest AMD chip show a one-third reduction in test time.