A semiconductor device has compensated threshold voltage and method of manufacture

The invention concerns a semiconductor device comprising in the channel region (6) first voids (7, 8) adjacent to the junctions (4, 5) which have a predetermined length Lp and a dopant concentration Np of a first conductivity type corresponding to the conductivity type of the substrate (1) dopant locally increasing the net substrate concentration and second voids (9, 10) superposed on the first voids having a length Ln and a dopant concentration Nn of a second conductivity type opposed to the first conductivity type satisfying the relationships Ln > Lp and Nn < Np and locally decreasing the net substrate concentration but without modifying the type of conductivity. The invention is applicable to a MOS transistor.