A simple and efficient VLSI sorting architecture

We have proposed a special-purpose VLSI architecture based on a new parallel sorting algorithm, the MM-SORT. The main ingredients of our design are three types of simple systolic structures: linear arrays, a sorting network and a complete binary tree, all operating in pipelined fashion. The basic processing elements are special storage cells, comparator/register pairs or ANDer/register pairs, and the interconnection degree of each processing element is bounded by a small constant. Due to the simplicity and regularity of this design, the proposed architecture is very suitable for VLSI implementation, and easy to be expanded.