Clock jitter compensation for current steering DACs
2006
Clock jitter is an important source of error in highspeed current-steering D/A converters. A technique to compensate these errors is introduced. Simulations show a significant reduction to clock jitter sensitivity for the example of a sigma delta DAC with an analog bandwidth (ABW) of 30 MHz clocked at 360 MHz.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
5
References
4
Citations
NaN
KQI