65nm technology for HEP: status et perspective
2014
The development of new experiments such as CLIC and the the foreseen Phase 2 pixel upgrades
of ATLAS and CMS have very challenging requirements for the design of hybrid pixel readout
chips, both in terms of performances and reliability. To face these challenges, the use of a more
downscaled CMOS technology compared to previous projects is necessary. The CERN RD53
collaboration is undertaking a R&D programme to evaluate the use of a commercial 65 nm technology
and to develop tools and frameworks which will help to design future pixel detectors. This
paper gives a short overview of the RD53 collaboration activities and describes some examples
of recent developments.
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