SRAM (Static Random Access Memory) and bit cell tracking method

The invention discloses an SRAM (Static Random Access Memory) and a bit cell tracking method. The SRAM is characterized in that a memory circuit comprises SRAM arrays, two tracking rows, two tracking columns, two dummy cells, two dummy SAs (sensor amplifiers), tracking bit lines and tracking word lines, wherein each memory circuit comprises SRAM bit cells which are arranged into rows and columns; the two tracking rows are respectively arranged on the upper parts of the two SRAM arrays; the two tracking columns are respectively arranged on two sides of the SRAM arrays; the two dummy cells are used for starting tracking bit line signals; the tracking bit lines penetrate through the tracking columns and are connected with dummy SAs; the tracking word lines penetrate through the tracking rows and are connected with the dummy cells. According to the SRAM, two tracking paths are utilized, the delay times of the two tracking paths are compared, and the larger delay time is utilized for controlling the sensor amplifier corresponding to a normal memory unit to be turned on. Thus, the SRAM has the main advantages that conditions of left and right BLs (bit lines), wLs (word lines) and cells can be simultaneously tracked, and influences of the process fluctuation, the voltage and the temperature on the read operation of the SRAM are reduced.