Towards development of a sidewall roughness standard

With the advent of FinFETs, precise control of sidewall roughness (SWR) has taken on a new importance in semiconductor manufacturing. The sidewall of the fin is the largest area of contact between the gate and channel. Controlling this contact requires precise and accurate metrology, which in turn requires calibration. Developing a calibration standard for sidewall roughness is therefore vital. This paper describes initial work towards creating such a standard, by demonstrating mutually supporting reference metrology on a patterned roughness feature. To create the standard, photoresist features were patterned using a programmed and controlled line edge roughness (LER). Initial roughness data was obtained by critical dimension atomic force microscopy (CD-AFM), a conformal film was then deposited to provide contrast for transmission electron microscopy (TEM), and full 3D roughness information across the entire sidewall was acquired by TEM tomography. The following serves as proof of concept for using these two measurements to check each other, moving towards development of a usable sidewall roughness standard.