Diagnosis Outcome Preview through Learning.

Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. However, diagnosis can be time-consuming and produce unuseful information for further investigation of yield loss. It would therefore be desirable to have a preview of diagnosis outcomes beforehand, which helps engineers allocate diagnosis resources in a more efficient way. In this work, random forest classification and regression techniques are used to predict three aspects of potential diagnosis outcomes: existence of multiple defects, diagnosis resolution, and runtime magnitude. Experiments on a 28nm test chip and a 90nm high-volume manufactured chip prove the efficacy of the proposed methodology - high accuracy for multiple defect (up to 0.86 accuracy and 0.93 AUC) and resolution prediction (up to 0.84 accuracy and 0.87 AUC), and over 98% of the runtime magnitude prediction is within the error of one magnitude. These results prove that the method can provide helpful information to guide prudent allocation of diagnosis resources.