Transaction-accurate interface scheduling in high-level synthesis
2012
The timing model for code presented to a high-level synthesis tool is an important factor in determining the level of abstraction which the HLS tool can support. There have been many attempts at defining a timing model. Here we survey some of the timing models that have been used, and present the transaction protocol model, used by Forte Design Systems' Cynthesizer, which has several advantages over previous timing models.
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