Scalability of partially depleted SOI technology for sub-0.25 /spl mu/m logic applications

The scalability of partially depleted (PD) SOI with a floating body has been evaluated to below the sub-0.25 /spl mu/m regime using transistors, ring oscillators and 4 Mb SRAMs as test vehicles. In this paper the speed and power performance of PD-SOI are compared to those of bulk for 1.8 V/sub-0.25 /spl mu/m logic applications. In addition, the 4 Mb SOI SRAM yield issues are revealed. Using the same transistor off-state leakage current limit criterion for both bulk and SOI, we conclude that PD-SOI with a floating body will provide no speed and insignificant power advantage over bulk for sub-0.25 /spl mu/m logic applications.