Multi-valued logic pass gate network using neuron-MOS transistors

A multi-valued logic (MVL) pass gate is an important element to configure multi-valued logic networks. Different from binary pass gates, multiple logical levels are required to be discriminated in MVL pass gates. In this paper, according to the feature of the threshold operation of a neuron MOS transistor (VMOS), two types of MVL pass gates using /spl nu/MOS are presented. One type, a CMOS MVL pass gate with VMOS down literal circuit, is composed of a CMOS pass gate and a VMOS threshold gate (/spl nu/MOS down literal circuit (DLC)). The discrimination between different MVL signals is realized by the threshold gate. Another type, a /spl nu/MOS hybrid pass gate, consists of a /spl nu/MOS transistor, a MOS transistor and a binary inverter. The VMOS transistor as used as a pass transistor, and the threshold discrimination is directly implemented by the VMOS pass gate. The latter is more compact than the former. The number of transistors and the layout area of the MVL network can be reduced by using /spl nu/MOS hybrid pass gates, while the bias setting is easier by using CMOS MVL pass gates. The common advantages of the proposed pass gates are low fabrication cost and possibility to build reconfigurable networks.