Electrostatic Discharge Protection For Embedded-Sensor Systems-On-a-Chip | NIST

AbstractThe MEMS microhotplate-based gassensor is an emerging technology that has cost and performance advantage compared to existing commercial gas sensing technologies. Microhotplate devices can be fabricated in standard CMOS technology enabling the use of low cost commercial foundries and monolithic integration of electronic circuits [1]-[2]. The MEMSbased gas sensor platform, heater power amplifier, signal conditioning, and control circuitry have recently been formulated as a virtual component (VC) conforming to the SoC design automation methodology facilitating design reuse and enabling the development of single chip gas sensing and classification solutions. The robustness of Embedded-Sensor (ES) Systemon-a-Chip (SoC) devices involve several design constrains that require a unique assessment. For instance, space-efficient electrostatic discharge (ESD) protection must be provided to protect the CMOS devices during the sensor micromachining processes in addition to the protection provided during normal operation and handling. In the post processing of the microhotplatebased gas sensor, there is a potential for an ESD event to occur at the sensing film electrodes prior to sensing film deposition. Fig. 1 depicts an SEM micrograph of a microhotplate-based gas-sensor showing ESD protected nodes. For such a gas-sensor SoC, ESD protection needs to be included not only in all the I/O pads but also in the electrodes of the sensor. Fig. 2 shows a schematic representation of an ESD protection scheme for a gassensor SoC. In this abstract, a reliable and space-optimized onchip ESD protection scheme for a gas-sensor VC is demonstrated. This ESD protection solution involves design of novel thyristor-type devices [3] implemented in the standard CMOS technology. The novel ESD protection scheme developed in this work includes ground referenced thyristor-type devices for 1) pad-level protection, 2) supply clamp, and 3) sensing electrodes. The I-V characteristics of the thyristor are designed to meet the constrains of the different components of the VC ESD protection by the proper selection of the internal dimensions (D, D2, L) shown in the cross-sectional view presented in Fig. 3. This property of the designed cell is illustrated by the TLP results for two thyristor devices with different dimension D presented in Fig. 4. References