Automated measurement of defect tolerance in mixed-signal ICs

Defect tolerance can improve system reliability and safety, and IC yield. This paper describes metrics for measuring defect tolerance of a mixed-signal circuit block within an IC. A general metric is defined for defect tolerance at the transistor-level, consistent with ISO 26262, and how it can be measured by an analog defect simulator, for digital and mixed-signal circuits, including those that have redundancy, error detection, and/or safe states. In effect, the analog defect simulator automatically implements failure modes and effects analysis (FMEA). It is especially useful for safety-oriented applications, like automotive ICs, but could also be useful for defect tolerance that improves IC yield. Digital and mixed-signal circuit examples illustrate usage.