Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process

Power Side-channel attacks are a serious class of attacks which targets the vulnerabilities in physical implementation of a design. One of the main challenges from the view of designers in the automated design flow is the lack of enough metrics, tools, and methods to automatically measure the level of security during the designing stages. Besides, current tools do not provide any hints or reports to the engineers about the locations or sources of side-channel vulnerabilities at pre-silicon deign stages. In this research, we will propose a framework called “PATCH”, which uses a statistical flow to precisely find the source nodes of the power side-channel leakage on any arbitrary register-transfer level (RTL) design. PATCH conducts security assessments on the design and reports its security status and vulnerable nets to the designer. This will provide flexibility to designers in order to apply required changes at early stages of the design process. Our results showed that PATCH can localize the sources of leakage in an efficient manner to be applicable in the ASIC design flow. In addition, it can optionally be accompanied with our Injection tool to automatically remediate leakage of information caused by vulnerable nets.