A 56 Gbps I/O Interface Design with Exact Power Source Simulation: Total I/O Circuit Design with over 28 GHz from Driver to Receiver Device Models

For over 20 GHz board level I/O interface circuits, the most serious problem is its high power consumption due to arrange adequate signal forming (pre-emphasis, adaptive equalizer, etc.) and timing adjust circuits that generally require 200 mW/lane for 28-56 Gbps interface. To reduce the power consumption, binary signal (Non Return to the Zero, NRZ) transmission system is fitted to eliminate easily above arrangements. Implementation with FR-4 printed circuit board (PCB) would be an only solution to tackle the problem of production cost of the transmission system. It is well known there are many technical challenges to realize over 200 mm transmission line for signal integrity even with 10 Gbps. With our simulation based analyses, we found that many studies have discussed signal integrity (SI) and power integrity (PI) issues only the range from MHz to 10 GHz of frequency. So it is necessary to consider the transmission parameters of the entire frequency range from direct current (DC) for high-speed I/O circuits especially in transistor level, because MOS devices need constant voltage for the switching operation. In this study, total I/O interface circuit, from CMOS driver through package interconnection to CMOS receiver, is examined mainly by simulation basis for 28 to 56 Gbps signaling. Three types of design were chosen as high speed differential driver / receiver device models, and the transmission characteristics were compared for the SI. One model is developed with TSMC's 65 nm IP, and other models are with 32 nm and 20 nm fin structure models of the Arizona State University's Predictive Technology Model (PTM). The PI parameters for the 40 mm and 200 mm wiring on PCBs, package with capacitors, and chip wiring including on-chip capacitor were studied to reach as possible as ideal voltage source by S-parameter simulation from DC to 100 GHz. We achieved the successful results of the target performance of 56 Gbps in some considered configuration. And the power consumption of our design can be achieved as low as 35 mW on this rate. The most significant aspect to realize our circuit design is the co-design among all I/O circuit parameters. The most effective parameters for our design methodology are: consistent conceptual consideration of power distribution network (PDN) transmission characteristics from DC to 100 GHz, and majority issue that is on-chip capacitor wiring configuration. We made the configuration of the PDF (PDN) at resonance frequency as high as 6.5 GHz. The driver device models examined in this study exhibited no explicit differences in performance up to 56 Gbps.