수직 채널 전계 트랜지스터 소자를 이용한 저전력 3진법 CMOS 구현

In this paper, we propose a novel structure of ternary CMOS(T-CMOS) composed of vertical channels induced by double gates (VCDG). The performance of the device is analyzed based on mixed-mode circuit simulation and compared with the performance of two types of T-CMOS built with conventional planar MOSFETs and FinFETs. Results from the numerical study indicate that static power of VCDG-type T-CMOS is 1.95 pW, which is less than that of planar MOSFET T-CMOS (3.25pW) and FinFET T-CMOS (12.35pW). In addition, the off-state current of the VCDG-type devices can be independent of gate bias even on devices with a few nm-scale, implying that stable T-CMOS operation can be achieved at high level of integration.