Towards sub-10 nm diameter InGaAs vertical nanowire MOSFETs and TFETs

The III-V vertical nanowire (VNW) MOSFETs is one of the candidates under consideration for CMOS technology beyond the 7 nm node [1]. This device architecture brings together the superior transport properties of III-V semiconductors [2] with the ultimate scalability of a vertical nanowire channel [3] where gate length, spacer thickness and contact length do not contribute to the footprint of the device [4]. With a similar geometry, III-V VNW TFETs potentially allow lower voltage operation and extreme high energy efficiency [5]. This is due to the TFET ability to achieve a subthreshold swing (S) below 60 mV/dec at room temperature (RT), a physical limit to MOSFETs [5]. III-V vertical nanowire MOSFETs and TFETs have been demonstrated by bottom-up [6-8] and top-down approaches [9-11]. Future ultra-scaled logic applications demand VNW FETs with sub-10 nm diameter [4]. Achieving this, remains an elusive goal. The difficulty lies in creating VNWs with a small diameter and a high aspect ratio, in contacting such thin VNWs, and altogether in addressing the integration challenges posed by such deeply scaled transistor structures. To our best knowledge, to date, the narrowest VNW transistor that has been claimed is an InAs/GaSb TFET with a diameter of 11 nm, but no electrical characteristics were shown [8]. In the Si system, 18 nm diameter VNW MOSFETs has been demonstrated [12].