A Novel Explicit Pulsed Dual Edge Triggered D Flip Flop

3 Abstract: This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation results overall improvements of 7.45%, 13.68% and 20.03% are observed in delay, power consumption and power delay product respectively.