High performance 3.3 and 5 volt 0.5-/spl mu/m CMOS technologies for ASICs

Two manufacturable high performance 0.5 pm CMOS technologies, one optimized for 5 V operation and the second optimized for 3.3 V operation, are presented. An improvement of 2 in circuit performance, 3.4 in packing density, 1.5 and 3.2 (for 5 and 3.3 V) in power consumption at constant speed, and 1.45 (for 3.3 V) in power consumption at maximum speed is achieved over AT&T's previous generation 0.9 /spl mu/m CMOS technology by device scaling, and aggressive interconnect and isolation design rules. >