Influence of polysilicon thickness on the microwave attenuation losses of the CPWs fabricated on polysilicon-passivated high-resistivity silicon substrates

In recent years, a high resistivity silicon (HR-Si) substrate is of interest as a substrate upon which integrated radio-frequency (RF) and millimeter wave circuits can be realized. Because the material have an inherent defect density, surface effect and resistivity degradation near the interface between an insulating oxide and a HR-Si substrate tend to overshadow the potentially low RF loss levels in HR-Si substrate. Fixed positive charges within the oxide attract free carriers near the substrate surface, leading to an accumulation or inversion layer on the silicon surface. Consequently, these free carriers act as the thin surface-channel at the Si/oxide interface, thus reducing the resistivity of the silicon surface and increasing the substrate loss. In fact, several surface passivation approaches have been used to overcome these shortcomings. For example, local resistivity can be enhanced by high-dose implantation (e.g, argon) to convert LR-Si substrate to HR-Si substrate [1], or a trap-rich passivation layer (e.g., polysilicon or amorphous silicon) between the oxide layer and the HR-Si substrate to prevent the carrier accumulation [2]. Polysilicon films deposited by LPCVD are the most widely used as a surface passivation layer on on HR-Si substrate and a thickness between 300nm and 400 nm were generally used. For HR-Si surface passivation application, the properties of LPCVD-deposited polysilicon (or amorphous silicon) are known to be significantly dependent on deposition conditions and annealing conditions [3].