A Fast Generation Algorithm of Huffman Encode Table for FPGA Implement

Data compression is a widespread used technique in digital signal processing system, and one of the most efficient approaches is Huffman coding. This paper proposed a new partially parallel algorithm, which combines Huffman tree building with traversing coding to accelerate the generation of Huffman coding table in Huffman encoder. Theoretical analysis and post-layout simulation results show that because of the partially parallel characteristic, the proposed algorithm can improve about 75% Huffman encoding speed, meanwhile is suitable for FPGA implement.