A compact broadband stacked medium power amplifier in standard 65 nm CMOS technology

This work presents the design and implementation of a fully integrated and compact broadband medium stacked power amplifier in standard 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack at the output to primarily increase the output impedance along with the output voltage swing. The load impedance is further optimized with a resistive feedback to the input active device which not only results in broadband operation but also helps in avoiding large and lossy broadband output matching network, resulting in a significant area reduction. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier works directly into a $$50\Omega $$50Ω load and shows a measured peak saturated output power from 13 to 8.5 dBm and a $$P_{1dB}$$P1dB of 7---4 dBm from 0.3 to 10 GHz. The drain and peak power added efficiency are 6.5 and 4.3 % under 4 V supply with DC power consumption of 160 mW. The measured small signal gain is around 9 dB with a gain ripple of ±1.5 dB till 7 GHz and 5.4 dB at 10 GHz, yielding a fractional bandwidth of 188 %. The measured load-pull ź1 dB, ź2 dB output power contours verify the optimum impedance around $$50\,\Omega $$50Ω. The active chip area is only 0.44 mm2.