A Highly Reliable FRAM (Ferroelectric Random Access Memory)

64 Mb FRAM with 1T1C (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The extrinsic failures can be linked to two activation energies: while one is 0.27 eV originated from oxygen-vacancy movements at the top interface and grain boundary in the ferroelectric films, the other is 0.86 eV caused by imperfection in either the top-electrode contact (TEC), or the bottom-electrode contact (BEC), or both, of the cell capacitor. As a result of applying novel schemes to remove the analyzed defectives, we have the FRAM with no bit failure up to 1000 hours over both high-temperature-operating-life (HTOL) and high-temperature-storage (HTS) tests