Memory unit and processing system

A memory unit and a processing system. The memory unit comprises at least one single-bit memory structure (101). Each single-bit memory structure (101) comprises four random access memories (RAMs): a first RAM (1011), a second RAM (1012), a third RAM (1013), and a fourth RAM (1014); two read-out ports: a first read-out port (101i) and a second read-out port (101j); two write-in ports: a first write-in port (101p) and a second write-in port (101q). The first read-out port (101i) is separately connected to the first RAM (1011) and the second RAM (1012), and is configured to read data stored in the first RAM (1011) and the second RAM (1012); the second read-out port (101j) is separately connected to the third RAM (1013) and the fourth RAM (1014), and is configured to read data stored in the third RAM (1013) and the fourth RAM (1014); the first write-in port (101p) is separately connected to the first RAM (1011) and the third RAM (1013), and is configured to write data into the first RAM (1011) and the third RAM (1013); and the second write-in port (101q) is separately connected to the second RAM (1012) and the fourth RAM (1014), and is configured to write data into the second RAM (1012) and the fourth RAM (1014).