Solutions to mitigate parasitic NPN bipolar action in high voltage analog technologies

This is a study of the parasitic NPN premature turn-on for high voltage BiCMOS technologies. In this work, we will investigate several methods to suppress its turn-on. Using TCAD and TLP we will investigate solutions based on increased well spacing, offset of wells, self-protection and beta reduction through highly doped base implant. We will also investigate the limitations associated with each of these solutions.