Register grouping for synthesis of clock gating logic

Clock gating logic is typically specified by designers in register transfer level (RTL). Its automatic synthesis is not only convenient but also complements RTL clock gating by extracting additional gating conditions. A key in automatic synthesis of clock gating logic is grouping registers that will share the same gating logic. A new grouping method based on iterative maximum weight matching is proposed. Clock gating implementation with the proposed method reduces power consumption by 40% on average with our test circuits.