Model-based scanner tuning for process optimization

Given the continually decreasing k1 factor and process latitude in advanced technology nodes, it is important to fully understand and control the variables that impact imaging behavior in the lithography process. In this joint work between TSMC and ASML, we use model-based simulations to characterize and predict the imaging effects of these variables and to fine-tune the scanner settings based on such information in order to achieve optimal printing results on a perreticle basis. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model construction. Simulations based on the calibrated model are subsequently used to predict the wafer impact of changes in tunable scanner parameters for all critical patterns in the product. The critical patterns can be identified beforehand, either experimentally on wafer, mask or through model simulations. A set of optimized scanner setting offsets, known as a "scanner tuning recipe" is generated to improve the imaging behavior for the critical patterns. We have demonstrated the efficacy of this methodology for multiple-use cases with selected ASML scanners and TSMC processes and will share the achieved improvements on defect reduction and yield improvements.