Timed Verification of the Generic Architecture of a Memory Circuit

Using a variant of Clariso-Cortadella's parametric method for verifying asynchronous circuits, we analyse some crucial timing be- haviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using the model of parametric timed automata and model checker HYTECH, we formally derive a set of linear con- straints that ensure the correctness of the response times of the memory. We are also able to infer the constraints characterizing the optimal setup timings of input signals. We have checked, for two different implemen- tations of this architecture, that the values given by our model match remarkably with the values obtained by the designer through electrical simulation.