Nanoscale Gate Stacks: From Atomic Defects to Device Performance

Concerted physical and electrical characterization of the gate stacks, which includes high dielectric constant materials and metal electrodes, has been performed in order to link atomic defects to the specific device electrical characteristics. It has been shown that defects in the SiO2 layer formed at the interface of the dielectric stack and the substrate plays a critical role in defining both performance and reliability of the high-k devices.