Marginal PCB assembly defect detection on DDR3/4 memory bus

A contemporary high-performance system board is a complex 3D object that may contain dozens of hidden layers, stacked microvias, high density interconnect, with all of the above not contributing to the ease of test and reliability. High-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in the case of now-ubiquitous DDR3 memories. Today, data transmission rates on the board may be reaching multigigabit ranges on a single channel. Such defects like dewetting, cold solder, head-in-pillow, voiding/crack in micro-via or excessive solder voids may result in system performance issues, increased error rates, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. In this work, we present a methodology aiming at systematic discovery of marginal defects, timing related faults and stability issues in board assembly's DDR3/4 data bus as part of the end-of-line testing in volume production environment. The methodology presented in this paper is based on an extended DDR memory controller in which we have converted the bus calibration mechanism into a fine-grain diagnostic instrument, which instead of masking marginal discrepancies (the normal case) would unveil and report them.