A Fault-Tolerant Router's Simulation and Design Based-FPGA in Network-on-Chips

Abstract Network-on-Chip has become a hot spot in the field of complex System-on-Chip for its effectiveness. The performance of NoC, to a large extent, depends on the router's structure. In this paper, we present a method based on fault-tolerant hardware structure to solve the problem of instability inhere in routers. We suggest adding bypass into routers and using a dynamic reconfigurable XY-YX routing algorithm; this solution shall ensure effective communications in NoC. Verilog language is used to describe all of the modules in Quartus II environment. We conduct the simulation experiment and area integrated, as well as accomplishes the overall modules’ design using Altera's FPGA. The experiment results show that our design can meet the needs of communication in NoC.