Frequency multiplier based on delayed phase-locked loop structure

The invention discloses a frequency multiplier based on a delayed phase-locked loop structure. The frequency multiplier based on the delayed phase-locked loop structure can solve the problem that the implementation cost of the existing frequency multiplication technical hardware based on the delayed phase-locked loop structure is too large. The frequency multiplier comprises a delayed phase-locked phase detection circuit, a voltage-controlled delay chain and an edge combination circuit, wherein the delayed phase-locked phase detection circuit is used for detecting the phase relationship between the input reference lock signal CLK0 and the output feedback clock signal CLKN of the voltage-controlled delay chain and generating the control voltage Vc which adjusts the delay of the voltage-controlled delay chain. The voltage-controlled delay chain comprises multiple delay units which are used for generating multiple multi-phase clock signals with equal phase differences. The edge combination circuit is composed of multiple frequency multiplier circuits and a two frequency-dividing circuit, wherein the multiple frequency multiplier circuits are used of conducting edge combination on multiple clock signals with equal phases so as to obtain a multiple frequency multiplication output signals, the two frequency-dividing circuit is used for conducting frequency-dividing operation on the multiple frequency multiplication output signals to obtain frequency multiplication out signals whose duty ratio is 50% (N/2).