ASIC Implementation of Linear Periodically Time Varying Filter by Thread Decomposition

This paper presents a low power architecture for linear periodically time varying (LPTV) filter by decomposing into finite computational threads. An N-tap, M period LPTV filter architecture is minimized into a single LTI filter by enabling the thread decomposition (TD) of the LPTV filtering operation. The proposed architecture is a generalization to the transposed form structure. A new insight, derived from TD enabled this generalization, which is otherwise not possible. Implementing the LPTV filter with multiplier less functional blocks based on binary common sub-expression elimination (BCSE) algorithm reduced the critical path delay. Experimental results show that the proposed design offers 48.9% reduction in area delay product (ADP) and 14.2% reduction in power delay product (PDP). The LPTV filtering operations in various applications can be realized with the proposed architecture. This work is the first attempt to the ASIC implementation of an efficient architecture for LPTV filter.