Optimization of J-V characteristic in diode array for phase change memory

In this paper, current density-voltage (J-V) characteristic of dual trench diode array have been investigated by both TCAD model and experimental method. It is shown that the arsenic concentration in buried N+ layer (BNL), epitaxial (EPI) layer thickness, and the dosage of P region in PN junction are expected to be the prominent factors responsible for both of the leakage and drive current performance according to TCAD simulation. By introducing the optimal siliconbased results, the 4×4 diode arrays were successfully manufactured by 40nm CMOS technology. The median values of drive and reverse leakage current densities are ~7.30×10 -2 A/μm 2 and 5.61×10 -9 A/μm 2 , respectively. The breakdown voltages (BVDs) of diode array are exceeding 6V, and the J on /J off ratios of ~10 9 , which can satisfy the requirements of phase change memory (PCM) applications.