ESD Interferences at the Chip- and Board-Level—Finding and Fixing Problems at the IC Level

Modern electronic device designs are becoming increasingly small and complex, requiring more and more integrated circuits (ICs). Such a development means that the standard practice of first testing a device’s ESD immunity, only during the final stages of development, is often ineffective. This is because any detected problems are, at this point, difficult, time consuming, and expensive to solve. Thus testing a device, or better yet its individual components, during the initial design cycle is more efficient and can be done using a special test setup to recreate the disturbance at the IC level. This letter focuses on the impact of IC behavior on electronic design, specifically, ESD characteristics and how they influence a device by influencing its ICs ( Fig. 1 ). The second part of this letter addresses further issues regarding these influences, such as electric- and magnetic-coupling. The simulation of coupling effects at the IC level are described and supplemented with an example ESD test. In this practical example, problems at the device and IC levels are described and identified using troubleshooting strategies, modifications are implemented, and their results are compared.