Address generator used for decoder of Turbo codes and LDPC codes

The invention belongs to the technical field of special instruction set processors, and particularly relates to an address generator used for a decoder of Turbo codes and LDPC codes. The address generator can generate addresses for the Turbo codes and the LDPC codes in various wireless communication standards including LTE/UMTS/WiMAX/WIFI and the like. A mixed structure is adopted for the address generator. The address generator mainly comprises an instruction memorizer, an instrument extraction module, a pre-decoding module, a multi-mode address calculation data channel, a data memorizer and the like, wherein the multi-mode address calculation data channel can be of different streamline structures according to configuration information, and address calculation is executed according to instructions. Compared with an ordinary address generator, the address generator is wider in coverage standard range and can generate addresses for the Turbo codes and the LDPC codes.