Chip-level reliability study of barrier engineered (BE) floating gate (FG) Flash memory devices

Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array (1Mb) was studied to provide chip-level reliability understandings. Finally, these results are compared with barrier engineered charge-trapping (CT) devices. Our results suggest that BE FG device is not promising in terms of serious reliability degradation and tail bits. Moreover, the speed enhancement is not better than using the conventional gate-coupling ratio (GCR) improvement or tunnel oxide scaling. On the other hand, CT devices do not have GCR and it need BE tunneling barrier to solve the erase and retention dilemma. We also prove that BE-SONOS device is immune to tail bits due to the nature of discrete trapped charge storage.