Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter

This paper presents the design of an oscillator-based true random number generator. The operation of the presented TRNG architecture is based on sampling a high-frequency oscillator output with a clock generated by a low-frequency noisy oscillator. The recycling folded cascode architecture was used for low power noise amplifier. A new method to achieve higher jitter in the low frequency oscillator is presented. The bit rate of the designed TRNG is 1.02 Mb/s. The circuit power consumption is $67 \mu \mathrm{W}$. The results of the simulations and statistical tests of the designed random number generator are also presented in this paper.