TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip

Power consumption has become one of the major challenges in current chip design. One effective low power technology, multiple supply voltages (MSVs), has succeeded in 2D network-on-chip (NoC) design. However, few researches considered the MSV in 3D NoC, especially application-specific 3D NoC. In this paper, a complete three-stage synthesis flow for MSV-driven application-specific 3D NoC is proposed, which involves all the issues of layer assignment, voltage level assignment, 3D NoC synthesis, floorplanning, and post-floorplanning adjustment. First, a unified model is presented considering both layer assignment and voltage level assignment, which achieves the best tradeoff between core power and communication power. After that, a 3D NoC synthesis method is proposed to assign network components (NCs) to each layer and generate interlayer connections while a two-stage floorplanning algorithm is used to determine the positions of both cores and NCs. Finally, a novel transitive closure graph-based post-floorplanning repacking algorithm is applied to further reduce the communication power without changing much of the floorplan. Experimental results show that the proposed method is very effective. Compared to traditional 3D NoC, the proposed method can reduce the core power by about 33.6%; compared to MSV-driven 2D NoC, the proposed method can reduce the communication power by about 52.6%.