Design of wide-range transceiver

This paper describes a wide-range transceiver with a range from 200Mb/s to 4Gb/s. A clock generator applied with Adaptive Frequency Calibrator (AFC) and a Clock Data Recovery Circuit (CDR) is proposed to ensure wide-range operation. The clock generator is designed to operate by compartmentalizing high speed and low speed modes at 2Gb/s as a basis. The AFC is applied to the high speed mode to generate low jitter clock, the Voltage Controlled Oscillator (VCO) is adjusted manually in low speed mode to satisfy wide-range operation. The Proposed CDR circuit uses coarse delay stage based on Delay Locked Loop (DLL) to which has an unlimited capture range, and fine delay stage based on phase interpolator (PI) which adjusts the delayed clock finely. It can guarantee a finer phase step in the wide operation. The designed wide-range transceiver uses 0.18µm CMOS process, and is simulated with the modeled channel and equalizer (EQ). The proposed transceiver achieves a BER of less than 10-10 with 27-1 PRBS. The worst phase delay step in the proposed transceiver is 13ps at 200Mb/s to 4Gb/s, and the average phase step is under approximately 10ps.